%0 Journal Article
%T PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED
%A Sreenivasa Rao.Ijjada
%A Ayyanna.G
%A G.Sekhar Reddy
%A Dr.V.Malleswara Rao
%J International Journal of VLSI Design & Communication Systems
%D 2011
%I Academy & Industry Research Collaboration Center (AIRCC)
%X Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.
%K Static CMOS Logic Dual rail domino logic
%K pseudo nmos
%K Low power.
%U http://airccse.org/journal/vlsi/papers/2211vlsics06.pdf