%0 Journal Article
%T A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER
%A Sudakar S. Chauhan
%A S. Manabala
%A S.C. Bose
%A R. Chandel
%J International Journal of VLSI Design & Communication Systems
%D 2011
%I Academy & Industry Research Collaboration Center (AIRCC)
%X In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented.CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, theswitching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation resultsshow that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supplyvoltage in TSMC 0.35 ¦Ìm process. Compared with the traditional flash ADC, this proposed method canreduce about 78% in power consumption.
%K CMOS Inverter
%K XOR gate based encoder
%K Flash ADC.
%U http://airccse.org/journal/vlsi/papers/2211vlsics08.pdf