%0 Journal Article
%T A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology
%A R.H.Talwekar
%A S.S Limaye
%J International Journal of VLSI Design & Communication Systems
%D 2012
%I Academy & Industry Research Collaboration Center (AIRCC)
%X A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as itprevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
%K Phase locked loop (PLL)
%K Delayed flip-flop (D-ff)
%K Phase frequency detector (PFD)
%K True signal phase clock (TSPC)
%K Voltage controlled oscillator (VCO)
%K Charge pump (CP)
%K Divider (Div)
%K Low pass filter (LPF).
%U http://airccse.org/journal/vlsi/papers/3512vlsics13.pdf