%0 Journal Article
%T Performance Evaluation of CDMA Router for Network-On-Chip
%A Anant W. Hinganikar
%A Mahendra A. Gaikwad
%A Rajendra M. Patrikar
%J International Journal of VLSI Design & Communication Systems
%D 2012
%I Academy & Industry Research Collaboration Center (AIRCC)
%X This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.
%K CDMA
%K Walsh Code
%K Router
%K NoC
%U http://airccse.org/journal/vlsi/papers/3312vlsics07.pdf