%0 Journal Article
%T Area, Delay and Power Comparison of Adder Topologies
%A R.Uma
%A Vidya Vijayan
%A M. Mohanapriya
%A Sharon Paul
%J International Journal of VLSI Design & Communication Systems
%D 2012
%I Academy & Industry Research Collaboration Center (AIRCC)
%X Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12¦Ìm 6metal layer CMOS technology using microwind tool.
%K Ripple Carry Adder
%K Carry Save Adder
%K Carry Increment Adder
%K Carry Select Adder.
%U http://airccse.org/journal/vlsi/papers/3112vlsics13.pdf