%0 Journal Article
%T A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes
%A B.R.B Jaswanth
%A R.V.S Rayudu
%A K.Mani babu
%A R.Himaja
%J International Journal of Technological Exploration and Learning
%D 2013
%I Nexus2world Publication
%X ¡ª This work presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flipflops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gatedclock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-drivertree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power.
%K Low Power Delay Buffer
%K Double Edge Triggered Flip Flop
%K Ring Counter.
%U http://ijtel.org/v2n2/(99-103)0202P05.pdf