%0 Journal Article
%T Low Power 4-2 Compressor for Arithmetic Circuits
%A Ms. Riya Garg
%A Mrs. Suman Nehra
%A Prof. B. P. Singh
%J International Journal of Recent Technology and Engineering
%D 2013
%I IJRTE
%X Most of the VLSI circuits used adders as a crucial portion, since they form the base element of all arithmetic functions. Increasing demand for portable equipments requires area and power efficient VLSI circuits. This paper presents 4-2 compressor using two different 8T full adder designs. The aim of this paper is to reduce the power consumption of 4-2 compressor without compromising the speed and performance. All pre-layout and post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 12.6 and compared in terms of power consumption, power-delay product (PDP) over various input voltages, temperatures and frequencies.
%K 2T (2 transistors)
%K 3T
%K 8T and PDP.
%U http://www.ijrte.org/attachments/File/v2i1/A0507032113.pdf