%0 Journal Article
%T High Performance Ethernet Packet Processor Core for Next Generation Networks
%A Raja Jitendra Nayaka
%A R. C. Biradar
%J International Journal of Next-Generation Networks
%D 2012
%I Academy & Industry Research Collaboration Center (AIRCC)
%X As the demand for high speed Internet significantly increasing to meet the requirement of large datatransfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP basednetwork products architecture must evolve and change. Application specific processors require highperformance, low power and high degree of programmability is the limitation in many general processorbased applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC)which performs all core packet processing functions, including segmentation and reassembly, packetizationclassification, route and queue management which will speedup switching/routing performance making itmore suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configuredfor use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulatedthe required functions in FPGA.
%K Ethernet
%K SoC
%K FPGA
%K NGN
%K LAN Router and Switches
%K IP networks
%K 1/10/20/40/100 Gigabit
%U http://airccse.org/journal/ijngn/papers/4312ijngn07.pdf