%0 Journal Article
%T FPGA implementation of IP packet segmentation and reassembly in internet router
%A Carevi£ż Marko
%A £żi£ża Zoran
%J Serbian Journal of Electrical Engineering
%D 2009
%I Technical Faculty of ?a?ak
%R 10.2298/sjee0903399c
%X Advanced packet scheduling algorithms in Internet routers work with fixed size cells. As IP packet length is not fixed, it is necessary to implement segmentation function for dividing IP packet in fixed sized cells. Also, it is necessary to reassemble original IP packet on output port of the router. Hardware implementation of these two functions will be presented in this paper.
%K IP packet
%K segmentation
%K reassembly
%K crossbar
%U http://www.doiserbia.nb.rs/img/doi/1451-4869/2009/1451-48690903399C.pdf