%0 Journal Article
%T High Density Four Transistor SRAM Cell with low Power Consumption
%A Sushil Bhushan
%A Shishir Rastogi
%A Mayank Shastri
%A Asso. Professor Shyam Akashe
%J International Journal of Computer Technology and Applications
%D 2011
%I Technopark Publications
%X This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus power during read/write operation reduced. Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained from this paper.
%K SRAM
%K read operation
%K write operation
%K power consumption
%U http://ijcta.com/documents/volumes/vol2issue5/ijcta2011020519.pdf