%0 Journal Article
%T MULTIPLE FAULT DIAGNOSIS FOR HIGH SPEED HYBRID MEMORY ARCHITECTURE
%A B. Kamala Soundari
%A M. Praveena£¿
%J International Journal of Computer Science and Mobile Computing
%D 2013
%I 
%X This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used toidentify permanent failures and automatic correction in all memories & circuits. The proposed approachoffers a simple test flow and does not require intensive interactions between a BIST controller and a tester.The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic.It is designed to meet requirements of at-speed test thus enabling detection of timing defects.
%K Built-in self-test (BIST)
%K deterministic partitioning
%K discrete logarithms
%K embedded read-only memory
%K fault diagnosis
%U http://ijcsmc.com/docs/papers/May2013/V2I5201322.pdf