%0 Journal Article
%T A Novel Architecture of LUT Design Optimization for DSP Applications
%A O. Anjaneyulu
%A Parsha Srikanth
%J International Journal of Advanced Electrical and Electronics Engineering
%D 2012
%I 
%X several architectures have been reported in the literature for memory based implementation of DSP algorithms involving orthogonal transforms and digital filters. The multiplication is major arithmetic operation in signal processing and in ALU¡¯s.the multiplier uses look-uptable (LUT) as memory for their computations. However, we do not find any significant work on LUT optimization for memory-based multiplication. A new approach to LUT design was presented, where only the odd multiple storage (OMS) scheme. In addition to that the anti symmetric product coding (APC) approach, the LUT size is reduced to half and provides a reduction. When APC approach is combined with the OMS technique, the two¡¯s complement operations could be simplified since the input address and LUT output could always be transformed into odd integers, and thus reduces the LUT size to one fourth of the conventional LUT.the proposed LUT multipliers for word size L=W=5 and 6 bits are coded in verilog and synthesized in Xilinx 13.4. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8-bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD) based multipliers. For 16-and 32-bit word sizes, respectively, it offers more than 30% and 50% of saving in area-delay product over the corresponding CSD multiplier.
%K Digital signal processing (DSP) chip
%K lookup- table (LUT)-based computing
%K Antisymmetric Product Coding (APC)
%K Odd multiple storage (OMS)
%K memory-based computing
%K very large scale integration (VLSI
%U http://irdindia.in/Journal_IJAEEE/PDF/Vol1_Iss2/1.pdf