%0 Journal Article
%T Review of VHDL Implementation of Quaternary Signed Adder System
%A Pranali S. Kamble
%A S.M.Choudhary
%J International Journal of Advanced Electrical and Electronics Engineering
%D 2012
%I 
%X The need for high speed digital circuits became more prominent as portable multimedia and communication applications incorporating information processing and computing. The drawback of modern computers lead to the deterioration in performance of arithmetic operations such as addition, subtraction, division, multiplication on the aspects of carry propagation time delay, high power consumption and large circuit complexity. This system explores the carry free n digits addition/subtraction as the carry propagation delay is most important factor regarding the speed of any digital system. In this paper, Quaternary signed digit (QSD) numbers whose radix is 4 are used in arithmetic operations to achieve the carry free arithmetic operations. The range of QSD number is from -3 to 3.In any n digit QSD number ,each digit can be represented by a number from the digit set [-3,-2,-1,0,1,2,3].Carry free addition and other arithmetic operations on large number of digits such as 64, 128, or more can be implemented with the fixed constant delay and less complexity. Modelsim SE-6.3f and Xilinx ISE-9.1i softwares are used for simulation of design of QSD adder system. Design is implemented using VHDL language and synthesized using Xilinx ISE-9.1i with Spartan 3 Field programmable Gate array (FPGA) Starter kit board
%K Carry free addition
%K Fast computing
%K QSD(Quaternary signed Digit)
%K VHDL
%K VLSI
%U http://irdindia.in/Journal_IJAEEE/PDF/Vol1_Iss1/8.pdf