%0 Journal Article
%T Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing
%A Sang Jeen Hong
%A Hee Yeon Kim
%A Seung-Soo Han
%J Transactions on Electrical and Electronic Materials
%D 2012
%I Korean Institute of Electrical and Electronic Material Engineers (KIEEME)
%X A number of surface mount technology (SMT) process variables including land design are considered for minimizingtombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip componentshave been reduced over the past years with their weights in milligrams, the torque that once helped self-centeringof chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly processvariables with respect to the tombstone defect by employing statistically designed experiment. After the statisticalanalysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effectsand interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statisticalanalysis was performed to investigate significant process variable for the purpose of process control in flexible printedcircuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printingprocess, chip-mounting process, and reflow process to minimize the tombstone defects.
%K Process optimization
%K Tombstone
%K Land design
%K Taguchi analysis
%K FPC
%U http://dx.doi.org/10.4313/TEEM.2012.13.3.129