%0 Journal Article
%T Parameter Optimization Performance Analysis of 4-Bit CMOS Layout for Adder
%A Amrita Shukla
%A Prof. Sandip Nimade
%A Prof. Vikas Gupta
%J International Journal of Engineering Innovations and Research
%D 2013
%I IJEIR
%X This paper we design 4-bit CMOS layout for 4-bit full adder with the help of half adder and other logic gates. In this paper we calculate power dissipation of gates and modules which we used in designing and also calculate the no. of transistors which were used in designing of gates. The result of simulation of adder layout is in Microwind2.
%K X OR
%K TOX
%K full adder
%K Microwind 2
%K VLSI
%U http://journals.indexcopernicus.com/fulltxt.php?ICID=1050576