%0 Journal Article
%T Conversion of an 8-bit to a 16-bit Soft-core RISC Processor
%A Ahmad Jamal Salim
%A Sani Irwan Md Salim
%A Nur Raihana Samsudin
%A Yewguan Soo
%J International Journal of Electronics Communication and Computer Technology
%D 2013
%I Nexus2world Publication
%X The demand for 8-bit processors nowadays is still going strong despite efforts by manufacturers in producing higher end microcontroller solutions to the mass market. Low-end processor offers a simple, low-cost and fast solution especially on I/O applications development in embedded system. However, due to architectural constraint, complex calculation could not be performed efficiently on 8-bit processor. This paper presents the conversion method from an 8-bit to a 16-bit Reduced Instruction Set Computer (RISC) processor in a soft-core reconfigurable platform in order to extend its capability in handling larger data sets thus enabling intensive calculations process. While the conversion expands the data bus width to 16-bit, it also maintained the simple architecture design of an 8-bit processor.The expansion also provides more room for improvement to the processor¡¯s performance. The modified architecture is successfully simulated in CPUSim together with its new instruction set architecture (ISA). Xilinx Virtex-6 platform is utilized to execute and verified the architecture. Results show that the modified 16-bit RISC architecture only required 17% more register slice on Field Programmable Gate Array (FPGA) implementation which is a slight increase compared to the original 8-bit RISC architecture. A test program containing instruction sets that handle 16-bit data are also simulated and verified. As the 16-bit architecture is described as a soft-core, further modifications could be performed in order to customize the architecture to suit any specific applications.
%K CPUSIM
%K FPGA
%K RISC processor
%K soft-core
%U http://www.ijecct.org/v3n2/(393-397)0302M30.pdf