%0 Journal Article
%T Implementation Of Low Power And Low Energy Synchronous Sapt Logic
%A Chitambara Rao.K
%A Nagendra.K
%A Sreenivasa Rao.Ijjada
%J International Journal of Distributed and Parallel Systems
%D 2012
%I Academy & Industry Research Collaboration Center (AIRCC)
%X This paper presents the design and implementation of a low-energy synchronous self timed logic topology using sense ampli er-based pass transistor logic (SAPTL). The SAPTL structure can realize for very lowpower computation by leakage current controlling networks with reduced supply voltages. The introduction of synchronous operation in SAPTL further improves energy-delay performance without a signi cant increase in hardware complexity. A simple XOR gate is implemented in SAPTL architecture. The power consumption of the SAPTL is less.
%K Low-voltage low-power logic styles
%K pass-transistor logic
%K VLSI circuit design.Low-leakage circuits
%K pass transistor
%K self-timing
%K sense ampli er-based pass transistor logic (SAPTL)
%K high-speed circuits
%K MOSFET logic devices
%K 90nm CMOS
%U http://airccse.org/journal/ijdps/papers/0112ijdps15.pdf