%0 Journal Article
%T A 802.11a Pulse-Swallow Integer-N Frequency Synthesizer
%A Cheng-Chan Tien
%A Tsung-Mo Mo Tien
%A Christina F. Jou
%J PIER    C
%D 2009
%I EMW Publishing
%R 10.2528/PIERC09021705
%X In this paper we will explain thoroughly a 802.11a pulse-swallow integer-N frequency synthesizer. The whole circuit is designed on chip except the loop filter. The reference frequency is set to 10 MHz and a pulse-swallow counter is designed for the purpose of controlling the dual-modulus divider (¡Â8/9). The frequency tuning range varies from 4.98 GHz to 5.73 GHz meanwhile the output power of the voltage-controlled oscillator is -13.5 dBm, and the phase noise measured at 1MHz is -126 dBc/Hz. The settling time of the closed loop is about 20 us, the total power dissipation is 26.35 mW with 1.8 V supply voltage. The chip is fabricated under TSMC CMOS 0.18 um.
%U http://www.jpier.org/pierc/pier.php?paper=09021705