%0 Journal Article
%T Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel
%A Arthur Spivak
%A Adam Teman
%A Alexander Belenky
%A Orly Yadid-Pecht
%A Alexander Fish
%J Sensors
%D 2012
%I MDPI AG
%R 10.3390/s120810067
%X Modern ˇ°smartˇ± CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage ˇ°smartˇ± image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.
%K CMOS
%K image sensor
%K low power
%K snapshot
%K SNR
%K strong inversion
%K sub-threshold
%K wide dynamic range
%U http://www.mdpi.com/1424-8220/12/8/10067