%0 Journal Article
%T A Use-Level Simulator for Tiled Chip Multiprocessor<br>一种分片式多核处理器的用户级模拟器
%A HUANG Kun
%A MA Ke
%A ZENG Hong-Bo
%A ZHANG Ge
%A ZHANG Long-Bing
%A <br>黄琨
%A 马可
%A 曾洪博
%A 张戈
%A 章隆兵
%J 软件学报
%D 2008
%I 
%X As the transistor resources and delay of interconnect wires increase,the tiled multi-core processor has been a new direction for multi-core processor.In order to thoroughly study new type processor and explore the design space of it,this paper designs and implements a user-level performance simulator for the tiled CMP architecture.The simulator adopts the directory-based Cache Coherence Protocol and the architecture of store-and-forward Network- on-Chip with Godson-2 CPU as the processing core model,and depicts out-of-order transacted requests and responses and conflictions of requests and their timing characteristics in detail.The simulator can be used to evaluate all kinds of important performance features of the tiled CMP(chip multiprocessor) architecture by running all kinds of sequential or parallel workloads,and thus provides a fast,flexible and efficient platform for architecture design of multi-core processor.
%K tiled CMP(chip multiprocessor)
%K simulator
%K network on chip
%K performance analysis
%K Godson-2 processor<br>分片式CMP(chip
%K multiprocessor)
%K 模拟器
%K 片上网络
%K 性能分析
%K 龙芯2号微处理器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=7735F413D429542E610B3D6AC0D5EC59&aid=5E8E6B0E06E61DC7A78C6A005FC61B96&yid=67289AFF6305E306&vid=2A8D03AD8076A2E3&iid=E158A972A605785F&sid=81A5772701933E75&eid=4AB97D697AC3192E&journal_id=1000-9825&journal_name=软件学报&referenced_num=0&reference_num=20