%0 Journal Article
%T Design for Testability and Implement Technology in ASIC Design<br>ASIC集成电路的可测性设计与技术实现
%A HAN Wei
%A JIANG Chuan
%A <br>韩威
%A 江川
%J 计算机科学
%D 2009
%I 
%X The hidden logic flaw and circuit fault are most difficult situation in implementation of ASIC.A comprehensive DFT technique can implement active detection and path tracing in SOC circuit,according to various circuits characteristic.The technique includes inside logic scan,memory built-in self test,boundary scan chain insertion and ATPG.It is proved by practice that the method mentioned above is able to increase the successful probability of developing a complex SOC design enormously.
%K SOC测试
%K 可测性设计
%K 主动测试技术
%K 故障模型
%K 测试向量自动生成
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=64A12D73428C8B8DBFB978D04DFEB3C1&aid=8518B672F00BA666BD5711BC4C0FCA58&yid=DE12191FBD62783C&vid=933658645952ED9F&iid=E158A972A605785F&sid=F50A8B5513721E1C&eid=8BB50A069C48D50B&journal_id=1002-137X&journal_name=计算机科学&referenced_num=0&reference_num=6