%0 Journal Article
%T Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
%A Wei-Wu Hu
%A Ji-Ye Zhao
%A Shi-Qiang Zhong
%A Xu Yang
%A Elio Guidetti
%A Chris Wu
%A <br>Wei-Wu Hu
%A Ji-Ye Zhao
%A Shi-Qiang Zhong
%A Xu Yang
%A Elio Guidetti
%A and Chris Wu
%J 计算机科学技术学报
%D 2007
%I 
%X This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.
%K general-purpose processor
%K superscalar pipeline
%K out-of-order execution
%K non-blocking cache
%K physical design
%K synthesis flow
%K bit-sliced placement
%K crafted cell
%K performance evaluation<br>精简指令集计算机
%K 分级存储器体系
%K 存储单元
%K 微处理器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=CBCDFFE5AEBDB1BF64D40DCE62FC79CC&yid=A732AF04DDA03BB3&vid=BC12EA701C895178&iid=CA4FD0336C81A37A&sid=CA4FD0336C81A37A&eid=2B25C5E62F83A049&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=3&reference_num=10