%0 Journal Article
%T The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT
%A Yan Zongfu
%A Liu Mingye
%A <br>Yan Zongfu
%A Liu Mingye
%J 计算机科学技术学报
%D 1996
%I 
%X This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.
%K High-level synthesis
%K RTL synthesis
%K technology mapping<br>电子电路设计自动化
%K 高电平合成
%K 实时语言合成
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=16CBA246425ED72A7507D99339C14DDA&yid=8A15F8B0AA0E5323&vid=708DD6B15D2464E8&iid=B31275AF3241DB2D&sid=12AD09BCF4A6E651&eid=1FA4E9C3E6E88FC8&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=0&reference_num=2