%0 Journal Article
%T High level synthesis for loop-based BIST<br>High Level Synthesis for Loop-Based BIST
%A Li Xiaowei
%A and Paul Y S Cheung
%A <br>LI Xiaowei
%A Paul Y.S. Cheung
%J 计算机科学技术学报
%D 2000
%I 
%X Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach.
%K built-in self-test (BIST)
%K at-speed testing
%K high-level synthesis
%K data path<br>硬件修改
%K BIST
%K 设计
%K 计算机
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=DAEF7C402F800351CFA0FDCF00EFEB2A&yid=9806D0D4EAA9BED3&vid=23CCDDCD68FFCC2F&iid=E158A972A605785F&sid=302684F6FB4B24FF&eid=3622B70F9C54A9CC&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=0&reference_num=16