%0 Journal Article
%T Algorithm and Implementation of Parallel Multiplication in a Mixed Number System
%A Luo
%A Yinfang
%J 计算机科学技术学报
%D 1988
%I 
%X This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinarybinary number and the symmetric redundant binary number.It is implemented with the multivalned logictheory,and 3-valued and 2-valued circuits are used.The 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed,simplicity and powerful functions.A 3-valued ECL thresholdgate can simultaneously produce six types of one-variable operations.The array multiplier,designed withthe algorithm and the circuits,is fast and simple,and is suitable for building LSI.It can be used in a high-speed computer just as an ordinary binary multiplier.
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=DD85530339E5613AC30A4BC4FF5EBA64&yid=0702FE8EC3581E51&vid=38B194292C032A66&iid=38B194292C032A66&sid=38685BC770C663F2&eid=527AEE9F3446633A&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=0&reference_num=0