%0 Journal Article
%T Microarchitecture of the Godson-2 Processor
%A Wei-Wu Hu
%A Fu-Xin Zhang
%A Zu-Song Li
%A <br>Wei-WuHu
%A Fu-XinZhang
%A Zu-SongLi
%J 计算机科学技术学报
%D 2005
%I 
%X The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18m CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.The work of this paper is supported by the National High Technology Development 863 Program of China (Grant Nos.2001AA111100 and 2002AA110010) and the Key Knowledge Innovation Project of Chinese Academy of Sciences
%K superscalar pipeline
%K out-of-order execution
%K branch prediction
%K register renaming
%K dynamic scheduling non-blocking cache
%K load speculation<br>显微结构
%K 超级标量管线
%K 转移预报
%K 处理器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=DDF4F63D592B12E284FA319C50BE14B4&yid=2DD7160C83D0ACED&vid=A04140E723CB732E&iid=0B39A22176CE99FB&sid=2B25C5E62F83A049&eid=2B25C5E62F83A049&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=23&reference_num=9