%0 Journal Article
%T Design and Verification of High-Speed VLSI Physical Design
%A Dian Zhou
%A Rui-Ming Li
%A <br>DianZhou
%A Rui-MingLi
%J 计算机科学技术学报
%D 2005
%I 
%X With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.
%K VLSI
%K physical design
%K floorplanning and placement
%K interconnect
%K delay
%K wire sizing
%K buffer insertion
%K power
%K order reduction
%K power grid
%K parameter extraction
%K clock distribution<br>VLSI
%K 结构设计
%K 互连
%K 线径号
%K 缓冲器插入
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=F57FEF5FAEE544283F43708D560ABF1B&aid=32439EA81989EE53F68033A3C48C30EB&yid=2DD7160C83D0ACED&vid=A04140E723CB732E&iid=0B39A22176CE99FB&sid=2922B27A3177030F&eid=31611641D4BB139F&journal_id=1000-9000&journal_name=计算机科学技术学报&referenced_num=0&reference_num=175