%0 Journal Article
%T Design of high-speed multiplier based on standard cell library extension<br>基于标准单元库扩展的快速乘法器设计
%A ZENG Xian-kai
%A ZHENG Dan-dan
%A YAN Xiao-lang
%A LV Dong-ming
%A GE Hai-tong
%A <br>曾宪恺
%A 郑丹丹
%A 严晓浪
%A 吕冬明
%A 葛海通
%J 计算机应用研究
%D 2012
%I 
%X This paper proposed a 17×17 bit signed digital multiplier. To improve the performance, the multiplier used modified Booth's recoding algorithm, a Wallace tree structure and design method based on standard cell library extension. It analyzed critical path using logical effort model, and by constructing cells with different driving capabilities, it implemented equal logical effort in each stage to achieve minimum path delay. Based on TSMC 90 nm standard cell library, generated an extended cell library, and implemented the layouts of multiplier respectively. Compared to standard cell library, the multiplier implemented with extended cell library achieved a performance improvement of 10.87%. Experimental results show that the semi-custom design methodology based on standard cell library extension can improve circuit performance effectively, which is especially appropriate for designs with large loads.
%K multiplier
%K standard cell library extension
%K modified Booth's recoding algorithm
%K Wallace tree
%K logical effort<br>乘法器
%K 标准单元库扩展
%K 改进的Booth编码算法
%K Wallace树
%K 逻辑功效
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=F886A295C1E57CC52B05C1461C0ABF3D&yid=99E9153A83D4CB11&vid=771469D9D58C34FF&iid=94C357A881DFC066&sid=F7E64A4EB9091FB5&eid=0420ACD7465FFFB2&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=0&reference_num=10