%0 Journal Article
%T Low-power mapping with delay optimized on NoC<br>延迟优化的片上网络低功耗映射*
%A XU Cheng
%A TAO Hai-yang
%A LIU Yan
%A LONG Bang
%A WANG Li-dong
%A <br>徐成
%A 陶海洋
%A 刘彦
%A 龙榜
%A 王立东
%J 计算机应用研究
%D 2009
%I 
%X NoC is an effective solution for challenges faced by the traditional bus-based SoC, such as power, delay, synchronization and signal integrity and so on. Power consumption and delay are important design constraints and performance metrics, and have optimizing space in all stages of design. Based on the ant colony optimization algorithm,the proposed approach reduced the power consumption and delay through the uniform distributed of the link concurrent communication events on NoC topology mapping phase. Simulation results show that solution compared to the link traffic balancing method can further optimize the power consumption and delay in topology mapping stage.
%K network-on-chip(NoC)
%K mapping
%K low-power
%K latency
%K ant colony optimization<br>片上网络
%K 映射
%K 低功耗
%K 延迟
%K 蚁群优化
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=3E5917DC03CE326B2EDC44F4ADE6AC06&yid=DE12191FBD62783C&vid=96C778EE049EE47D&iid=F3090AE9B60B7ED1&sid=BDC707DB90449563&eid=6E30A65D6DD5D131&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=1&reference_num=17