%0 Journal Article
%T A Low Power Design of DSP Processor Bus<br>一种降低DSP芯片总线功耗的设计方案
%A CHENG Song
%A WANG Dong-lin
%A LI Li-jian
%A <br>成嵩
%A 王东琳
%A 李立健
%J 计算机应用研究
%D 2005
%I 
%X A novel low-power bus design for DSP processor is presented in the paper. The design integrates a new bus encoding for low-power and bus-Invert code. The design is proposed that significantly reduce transition activity on data and address buses. The experiments demonstrate significant reduction in transition activity of up to 21.56 % in data bus and up to 40. 29% in address bus.
%K SoC
%K Buses
%K Low Power<br>SoC
%K 总线
%K 低功耗
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=4A84426F7379509E&yid=2DD7160C83D0ACED&vid=BC12EA701C895178&iid=F3090AE9B60B7ED1&sid=67969BA850333433&eid=228A710F49B6CE58&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=0&reference_num=6