%0 Journal Article
%T Design and implementation of parallel CISC instruction decoder<br>并行CISC指令译码器的设计与实现*
%A ZHANG Jun
%A FAN Xiao-ya
%A ZHANG Meng
%A <br>张骏
%A 樊晓桠
%A 张萌
%J 计算机应用研究
%D 2007
%I 
%X The defect of serial decoder scheme in x86 series microprocessor was slow speed and low efficiency. To overcome these problems, proposed a parallel decoder scheme. Divided the whole decoder process into two stages, which were length decode and address decode. These two stages decoded instructions in pipeline mode. The length of an instruction without prefix could be figure out in one clock. Any two instructions could be decode in parallel. So, improved the efficiency of decoder. Used Verilog-HDL to describe the whole design, and used SYNOPSYS-DV to synthesize in SMIC CMOS 0. 18-library. The results reach the design specification.
%K instruction set
%K microprocessor
%K decoder
%K CISC<br>指令集
%K 微处理器
%K 译码器
%K 复杂指令系统计算机
%K 并行译码
%K CISC
%K 指令译码器
%K 设计方案
%K decoder
%K instruction
%K parallel
%K implementation
%K 完全
%K 结果
%K 综合
%K 工艺库
%K SMIC
%K CMOS
%K 描述
%K 使用
%K 支持
%K 成长度
%K 情况
%K 前缀
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=C793235A4E87B8F69D260B9319E135B6&yid=A732AF04DDA03BB3&vid=B91E8C6D6FE990DB&iid=708DD6B15D2464E8&sid=1E41DF9426604740&eid=974CBB04624305A1&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=0&reference_num=5