%0 Journal Article
%T Synchronous Design of Enhanced Parallel Port<br>EPP并行通信接口同步设计
%A LIANG Jie
%A GAO De-yuan
%A ZHANG Sheng-bing
%A DUAN Ran
%A <br>梁婕
%A 高德远
%A 张盛兵
%A 段然
%J 计算机应用研究
%D 2005
%I 
%X Due to the facts that it is more difficult to control the timing of asynchronous devices and less support from EDA tools compared with synchronous device, presents a design of synchronous Enhanced Parallel Port(EPP) based on FSM, which makes the timing of EPP more clear and controllable, and the circuits more stable and reliable.The method can also be applied to designing synchronous PS/2, Extended Capabilities Port(ECP), etc.
%K Enhanced Parallel Port(EPP)
%K Parallel Interface
%K Finite State Machine (FSM)<br>EPP
%K 并行接口
%K 状态机
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=038B1445099CE403&yid=2DD7160C83D0ACED&vid=BC12EA701C895178&iid=B31275AF3241DB2D&sid=E0F6F365E4766526&eid=FEF02B4635FE8227&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=0&reference_num=3