%0 Journal Article
%T Latency Analysis of an Improved Floating point Fused Multiply add<br>一种改进的浮点乘加器结构的延时分析*
%A JIN Zhan peng
%A SHEN Xu bang
%A TIAN Fang fang
%A <br>靳战鹏
%A 沈绪榜
%A 田芳芳
%J 计算机应用研究
%D 2006
%I 
%X This thesis estimate the delay of the critical path of an improved floating point fused multiply add (MAF) at a qualitative level, and compare it with the basic MAF implementation.
%K Floating point Fused Multiply add
%K Critical Path
%K Leading zero
%K Latency<br>浮点乘加器
%K 关键路径
%K 前导零
%K 延时
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=4A727689A7164FF46931A7E46581A176&yid=37904DC365DD7266&vid=EA389574707BDED3&iid=B31275AF3241DB2D&sid=CD775AE9DDBD7B53&eid=117F81797AB182FC&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=0&reference_num=0