%0 Journal Article
%T Design and Implementation of a Parallel Multiplier<br>一种并行乘法器的设计与实现*
%A WANG Xin-gang
%A FAN Xiao-y
%A LI Ying
%A QI Bin
%A <br>王新刚
%A 樊晓桠
%A 李瑛
%A 齐斌
%J 计算机应用研究
%D 2004
%I 
%X Based on the characteristic of complement code,the traditional Booth2 algorithm has been modified.When it computes the sum of partly product,a balanced 4-2 compressor and a special adder are used to form Wallace tree and to compute the sum of the result of Wallace tree respectively.The circuit is described using Verilog HDL language and synthesized by Design analyzer.Finally,it is shown that this scheme has higher speed and bigger scale than traditional CSA array multiplier.
%K Parallel Multiplier
%K Booth2
%K Wallace Tree<br>并行乘法器
%K Booth2
%K Wallace树
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=8240383F08CE46C8B05036380D75B607&jid=A9D9BE08CDC44144BE8B5685705D3AED&aid=D000731CBC973A04&yid=D0E58B75BFD8E51C&vid=659D3B06EBF534A7&iid=DF92D298D3FF1E6E&sid=5E25104E99903E8A&eid=205BE674D84A456D&journal_id=1001-3695&journal_name=计算机应用研究&referenced_num=1&reference_num=5