%0 Journal Article
%T 0.5 ¦ÌW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 ¦Ìm Fully Depleted Silicon-on-Insulator (FDSOI) Process
%A Piotr Olejarz
%A Kyoungchul Park
%A Samuel MacNaughton
%A Mehmet R. Dokmeci
%A Sameer Sonkusale
%J Journal of Low Power Electronics and Applications
%D 2012
%I MDPI AG
%R 10.3390/jlpea2020155
%X We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 ¦ÌW at 0.6 V and 46.6 dB/45.01 KHz/10.8 ¦ÌW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 ¦ÌW at 0.4 V and 53 dB/1.4 KHz/1.6 ¦ÌW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.
%K sub-threshold
%K weak inversion
%K analog design
%K OTA
%K low power
%K FDSOI
%U http://www.mdpi.com/2079-9268/2/2/155