%0 Journal Article
%T Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS
%A David Bol
%J Journal of Low Power Electronics and Applications
%D 2011
%I MDPI AG
%R 10.3390/jlpea1010001
%X Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10กม, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.
%K digital CMOS circuits
%K ultra-low power
%K subthreshold logic
%K variability
%K leakage currents
%K yield
%U http://www.mdpi.com/2079-9268/1/1/1