%0 Journal Article
%T Energy Efficient Supply Boosted Comparator Design
%A Suat U. Ay
%J Journal of Low Power Electronics and Applications
%D 2011
%I MDPI AG
%R 10.3390/jlpea1020247
%X This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1£¿V operation with a wide input range due to high threshold voltage (high-V TH) of MOS transistors (+0.8 V/£¿0.9 V). Despite this, the proposed comparator operates sub-1£¿V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.
%K supply boosting
%K mixed-signal design
%K low-voltage design
%K comparator
%U http://www.mdpi.com/2079-9268/1/2/247