%0 Journal Article
%T FPGA-based Joint Design of LDPC Encoder and Decoder<br>基于FPGA的LDPC码编译码器联合设计
%A Yuan Rui-jia Bai Bao-ming
%A <br>袁瑞佳
%A 白宝明
%J 电子与信息学报
%D 2012
%I 
%X A joint design of FPGA-based encoder and decoder of LDPC codes is proposed. In this new design, the LDPC encoder and decoder share the same parity-check calculation circuit and the same RAM block, resulting in significantly reduced resource consumption in hardware implementations. The design is suitable for encoding and decoding realizations based on parity-check matrix. It can accommodate full-parallel architectures both for the encoder and decoder, or partial-parallel architectures that are widely adopted nowadays. Furthermore, various decoding algorithms such as the sum-product and the min-sum algorithms can be adopted in this design. The proposed joint design method is applied to design the enoder and decoder of two different groups of LDPC codes, both with a partial-parallel structure. The implementation based on an Xinlinx XC4VLX80 FPGA shows that the designed encoder and decoder can work well in a parallel way, and only consumes slightly more hardware resources than that required by a single decoder. As a result, the proposed design can effectively reduce the hardward consumption without sacrificing the throughput.
%K Digital communication system
%K LDPC code
%K Encoder
%K Decoder<br>数字通信系统
%K LDPC码
%K 编码器
%K 译码器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=3B8BF30E16FD5CB0D29DEE1BC5CC6025&yid=99E9153A83D4CB11&vid=339D79302DF62549&iid=CA4FD0336C81A37A&sid=16D8618C6164A3ED&eid=1AE5323881A5ECDC&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=11