%0 Journal Article
%T High-Speed Hardware Implementation for GCM in IEEE802.1AE<br>IEEE802.1AE中GCM的高速硬件实现
%A Zhao Jing-jing
%A Li Li
%A Pan Hong-bing
%A Xu Jun
%A Wu Zhi-gang
%A Lin Jun
%A <br>赵晶晶
%A 李 丽
%A 潘红兵
%A 许 俊
%A 吴志刚
%A 林 军
%J 电子与信息学报
%D 2010
%I 
%X This paper presents a high-speed GCM architecture, which is suitable for IEEE 802.1AE protocol. The core modules of GCM include AES and Ghash. In Ghash module, a new parallel multiply-adder is proposed, which can handle several sets of data at the same time without knowing the total number of data blocks in advance. To support constant key changes in each clock cycle, loop-unrolling structure is used in KeyExpansion module of AES. A GCM encryptor design example with 2-parallel Ghash is implemented and the performance is evaluated by utilizing Fujitsu 0.13 μm 1.2 V 1P8M CMOS technology and a very high throughput of 97.9 Gbps is obtained with 547 Kgates, operating at 764.5 MHz.
%K IEEE802
%K 1AE protocol
%K Galois/Counter Mode(GCM) algorithm
%K AES algorithm
%K Key Expansion
%K Ghash function
%K Hardware implementation<br>IEEE802.1AE协议
%K GCM算法
%K AES算法
%K 密钥扩展
%K Ghash函数
%K 硬件实现
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=3E5A11D60647832E5DC397A8A76069E8&yid=140ECF96957D60B2&vid=9971A5E270697F23&iid=B31275AF3241DB2D&sid=6F185A924223F19E&eid=DEEC1AC3B6D3EB96&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=12