%0 Journal Article
%T A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes<br>同步部分并行结构的准循环LDPC码译码器
%A Xu En-yang Jiang Ming Zhao Chun-ming
%A <br>许恩杨
%A 姜明
%A 赵春明
%J 电子与信息学报
%D 2008
%I 
%X Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper. In the decoder, the check node process units and variable node process units work concurrently, where the new generated soft information is used in advance during the iteration process to accelerate the convergence speed. Furthermore, differential evolution is utilized to optimize the start positions of node process units in order to achieve better performance. Simulation results show that the proposed scheme outperforms others both in performance and complexity, and is very suitable for the implementation of high speed decoders.
%K Low-Density Parity-Check (LDPC) codes
%K Decoder
%K Synchro partially parallel architecture<br>低密度奇偶校验(LDPC)码
%K 译码器
%K 同步部分并行结构
%K 同步
%K 部分并行结构
%K 准循环
%K LDPC
%K Codes
%K 码译码器
%K Parallel
%K Architecture
%K 复杂度
%K 译码性能
%K 方案
%K 仿真结果
%K 优化
%K 起始位置
%K 方法
%K 演化
%K 差分
%K 收敛速度
%K 迭代过程
%K 使用
%K 信息能
%K 中新
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=68D970442FC4052C5D3173433EDC7EAE&yid=67289AFF6305E306&vid=340AC2BF8E7AB4FD&iid=DF92D298D3FF1E6E&sid=2AAEC1E50A125188&eid=A5467BD7DE258358&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=10