%0 Journal Article
%T Reconfigurable Clustered Architecture of Block Cipher Processor<br>分组密码处理器的可重构分簇式架构
%A Meng Tao Dai Zi-bin
%A <br>孟涛
%A 戴紫彬
%J 电子与信息学报
%D 2009
%I 
%X This paper presents the reconfigurable clustered architecture of block cipher processor. Appointed by instructions, the data-path of this architecture can be dynamically configured to be three modes, which includes 4clusters, 2clusters and single cluster mode. In different mode, different operations can be done, which improves the flexibility of this processor. Basing on clustered architecture, Explicit-decomposition low-power-design method is presented, which can reduce the power by 36.1%. With 5stages pipeline and wave-pipeline, this processor can work in a high rate. And the performances of AES/DES/IDEA reach 689.6Mbit/s, 400Mbit/s, 416.7Mbit/s.
%K Block cipher
%K Clustered architecture
%K Reconfigurable computing
%K Low-power-design
%K Pipeline<br>分组密码算法
%K 分簇式架构
%K 可重构计算
%K 低功耗设计
%K 流水线
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=F125914AF6028445AFF535435E74314C&yid=DE12191FBD62783C&vid=4AD960B5AD2D111A&iid=0B39A22176CE99FB&sid=FB36B1C076A263FA&eid=522844664D9E629A&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=16