%0 Journal Article
%T Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit<br>版图面积受限POR电路中复位延迟问题的研究
%A Qu Xiao-gang
%A Yang Hai-gang
%A <br>屈小钢
%A 杨海钢
%J 电子与信息学报
%D 2010
%I 
%X To solve the problem of an excessive area required to implement milliseconds reset time with resistance and capacitance in POR (Power-On Reset) circuit, an area-efficiency delay circuit based on an exponential time-extending technique is proposed in this paper. The circuit utilizes asynchronous frequency division to increase delay exponentially, using the period of signal which ring oscillator generates as a reference delay unit and is capable of implementing milliseconds delay for minimum silicon area. It is used to generate a long enough reset time in the POR circuit. To verify the technique, the circuit is designed and fabricated in the SMIC 0.18 μm process. According to the measured results, the circuit typically achieves 0.91 ms delay with an area of 172 μm×75 μm and 54.9 ms delay with an area of 172 μm×95 μm. As compared with RC method, the circuit can respectively save at least 82.8% and 97% layout area for implementing the same delays.
%K VLSI
%K ASIC
%K PLD (Programmable Logic Device)
%K Delay circuit
%K Power-On Reset (POR) circuit<br>VLSI
%K ASIC
%K 可编程逻辑器件
%K 延时电路
%K 上电复位电路
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=EAF4F52CE0B480D837C26528FF193459&yid=140ECF96957D60B2&vid=9971A5E270697F23&iid=B31275AF3241DB2D&sid=79D108842269596A&eid=C919C6DD1115AFC0&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=9