%0 Journal Article
%T Optimization Design of Digital Quadrature Demodulation Receiver Based on FPGA<br>基于FPGA的数字化正交解调接收机最优设计
%A Qiu Zhao-kun
%A Ma Yun
%A Wang Wei
%A Chen Zeng-ping
%A <br>邱兆坤
%A 马 云
%A 王 伟
%A 陈曾平
%J 电子与信息学报
%D 2006
%I 
%X Under certain conditions, combining the polyphase filtering structure of decimation filter, optimum design method of quadrature demodulation receiver, which owns decimation structure. With the put forward an same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly 4 times than it implemented in direct way. Finally the design instance is given.
%K FPGA<br>正交解调
%K 多项滤波
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=46CE22B882D91F21&yid=37904DC365DD7266&vid=D3E34374A0D77D7F&iid=CA4FD0336C81A37A&sid=2001E0D53B7B80EC&eid=1AE5323881A5ECDC&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=7