%0 Journal Article
%T The Design of Monolithic CMOS Clock Recovery Circuit<br>CMOS集成时钟恢复电路设计
%A Li Xue-chu
%A Gao Qing-yun
%A Chen Hao-qiong
%A Qin Shi-cai
%A <br>李学初
%A 高清运
%A 陈浩琼
%A 秦世才
%J 电子与信息学报
%D 2007
%I 
%X A monolithic clock recovery circuit is proposed in this paper. The frequency of the recovered clock is 125MHz. By using of some compensation methods, such as current subtraction technology, the gain of the VCO is greatly diminished, as a result the chip area is reduced also without sacrificing the noise performance of the recovered clock. This design is implemented by a 0.25μm standard CMOS technology. The active chip area is less than 0.2mm2, and the power consumption is only 10mW. The simulation results in different temperature and process condition indicate that the phase error of the recovered clock is less than 200ps and the peak-to-peak jitter is less than 150ps. A 100MHz PHY with the proposed clock recovery circuit inside is taped out and tested. The test result shows that the clock recovery circuit works properly.
%K Clock recovery
%K 100MHz PHY
%K Hogge phase detector
%K PLL<br>时钟恢复
%K 100MHz
%K PHY
%K Hogge鉴相器
%K 锁相环
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=28A01807AECFA841&yid=A732AF04DDA03BB3&vid=771469D9D58C34FF&iid=B31275AF3241DB2D&sid=592CC3414B588215&eid=D56713C22DA9FDE8&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=5&reference_num=5