%0 Journal Article
%T STATE TRANSITION REDUNDANCE IDENTIFICATION<br>时序电路的冗余状态变换确认研究
%A He Xinhua
%A Cai Hongliu
%A Wang Weifeng
%A <br>何新华
%A 蔡红柳
%A 王维峰
%J 电子与信息学报
%D 1999
%I 
%X The BDD (Binary Decision Diagram) is very important for representing synchronous circuits. After analyzing and reducing the BDD, the state traversing is proposed on the basis of collapsing of input, routes and states on STG. Finally, the verification for the non-reset circuits has been described.
%K Test generation
%K Verification
%K Finite-state-machines<br>测试生成
%K 验证
%K 有限状态机
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=16FC19140A33CD2A7DA9E830E50DB7EC&yid=B914830F5B1D1078&vid=659D3B06EBF534A7&iid=CA4FD0336C81A37A&sid=A8DE7703CC9E390F&eid=3986B25773CB6C30&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=2