%0 Journal Article
%T The Design of DPLL for Low SNR Signals with Large Frequency Offset<br>一种大频偏和低信噪比条件下的全数字锁相环设计
%A Shuai Tao
%A Liu HuiJie
%A Liang XuWen
%A Yang GenQing
%A <br>帅涛
%A 刘会杰
%A 梁旭文
%A 杨根庆
%J 电子与信息学报
%D 2005
%I 
%X The digital phase-locked loops design is a key technology for carrier and bit synchronization in coherent demodulation digital receiver. Large frequency offset and low SNR add more difficulties of the loop design from two different ways. Based on this condition, aim at fast acquisition and tracking, a method of digital loop parameter algorithm is proposed in this paper and some useful conclusions are given.
%K Digital Phase-Locked Loop(DPLL)
%K Doppler frequency offset
%K Low SNR
%K Synchronization<br>数字锁相环
%K 多普勒频偏
%K 低信噪比
%K 同步
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=8FD6F486206565F2&yid=2DD7160C83D0ACED&vid=DB817633AA4F79B9&iid=5D311CA918CA9A03&sid=83B38B9EF611BE13&eid=E477FFDBDE309A4B&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=6&reference_num=8