%0 Journal Article
%T VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS<br>时序电路的状态验证研究与设计
%A He Xinhua
%A Lu Changling
%A Gong Yunzhan
%A <br>何新华
%A 吕昌龄
%A 宫云战
%J 电子与信息学报
%D 1997
%I 
%X It is very effective that use BDD to describe the synchronous circuits. This paper has proposed the reducing way for BDD in order to collapse the number of inputs, routes and states. Based on the features of circuit, several heuristic methods that speed up verification are presented.
%K Binary Decision Diagram(BDD)
%K Node
%K Collapsing
%K Stata Transition Graph(STG)<br>二元判定图
%K 节点
%K 压缩
%K 状态变换图
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=B40A60A8B9E9267F6887F5D71EEBC953&yid=5370399DC954B911&vid=2A8D03AD8076A2E3&iid=E158A972A605785F&sid=640CCB6E396307A8&eid=FD207D3C5E9776FA&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=3