%0 Journal Article
%T THE LOGIC SYNTHESIS OF MULTIVALUED SYMMETRIC FUNCTION BASED ON BINARY FULL-ADDER<br>多值对称函数基于二值全加器的电路实现
%A Chen Xiexiong
%A Shen Jizhong
%A <br>陈偕雄
%A 沈继忠
%J 电子与信息学报
%D 1996
%I 
%X This paper discusses the definition and properties of multivalued symmetric functions, and points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj corresponding to j will certainly be a symmetric function, and it may be expressed as the sum-of-products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the logic synthesis circuit realization for the multivalued symmetric functions based upon full-adders is proposed.
%K Multivalued logic
%K Symmetric functions
%K Logic design<br>多值逻辑
%K 对称函数
%K 逻辑设计
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=4D553BA0DC2DF67F4007C8D53BFB1041&yid=8A15F8B0AA0E5323&vid=13553B2D12F347E8&iid=94C357A881DFC066&sid=640CCB6E396307A8&eid=323E8A365B085E0B&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=5