%0 Journal Article
%T A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE<br>一种级联结构的高阶全数字锁相环
%A Shi Fujiang
%A Lin Xiaokang
%A Feng Zhongxi
%A <br>史富强
%A 林孝康
%A 冯重熙
%J 电子与信息学报
%D 1999
%I 
%X A high order all digital phase locked loop with tandem structure is presented. A 2-order all digital PLL is implemented and its performance is verified by simulation. An example is given for SDH 2048Kb/s tributary recovery. Its performances are simulated and compared with the theoretical analysis.
%K All digital PLL
%K Pointer leaking
%K Jitter<br>全数字锁相环
%K 指针泄漏
%K 抖动
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=EFC0377B03BD8D0EF4BBB548AC5F739A&aid=20ABDFCD4A2B7ACE636C6C757118027F&yid=B914830F5B1D1078&vid=659D3B06EBF534A7&iid=94C357A881DFC066&sid=DB7B2C790D19BE6E&eid=9107B2E171152411&journal_id=1009-5896&journal_name=电子与信息学报&referenced_num=0&reference_num=8