%0 Journal Article
%T Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer<br>
%A HO Chi-Hon
%A LIAO Chien-Nan
%A CHIEN Feng-Tso
%A TSAI Yao-Tsung
%A <br>
%J 中国物理快报
%D 2009
%I 
%K 73
%K 40
%K Ty
%K 73
%K 61
%K Cw<br>
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=6E709DC38FA1D09A4B578DD0906875B5B44D4D294832BB8E&cid=47EA7CFDDEBB28E0&jid=E27DA92E19FE279A273627875A70D74D&aid=F52400F91F1A194BC3DF1D4DA9E70C1F&yid=DE12191FBD62783C&vid=96C778EE049EE47D&iid=CA4FD0336C81A37A&journal_id=0256-307X&journal_name=中国物理快报&referenced_num=0&reference_num=0